1. Field of the Invention
The invention relates to the fabrication of a very large scale integrated circuit including both protected drain-source variable threshold N-channel silicon gate nonvolatile memory elements and fixed threshold devices.
2. Description of the Prior Art
During recent years extensive progress has been made in the development of EAROM technology. However, all of the existing prior art devices use aluminum gate P-channel technology, which limits the read access time of the memory to one microsecond and the bit density to between 4 and 8 kilobits per chip. To meet the performance requirements for many systems, a read access time of less than 3 hundred nanoseconds must be achieved; in addition, bit densities must be improved by at least a factor of 4 (i.e. 16 kilobits--32 kilobits per chip).
In prior art MNOS memory devices, the variable threshold transistor contains a thin gate oxice layer composed of silicon dioxide (typically 25 A thick) covered by a silicon nitride layer (typically 350 A thick) and then by an aluminum or polysilicon electrode. The article entitled "Threshold-Alterable Si-Gate MOS Devices," authored by Peter C. Y. Chen and published in Vol. ED-24, No. 5, May 1977 of the IEEE Transactions on Electron Devices (pp. 584-586), discusses such memory devices. The thin silicon dioxide gate insulator layer is necessary to achieve the memory function with nonvolatile storage in the silicon nitride layer. A problem, however, arises in that the thin silicon dioxide/silicon nitride layer results in a very low breakdown voltage BV.sub.DSS (e.g., less than 20 volts). Unfortunately, the device requires a minimum of 25 volts to effectively write or erase the charge stored in the silicon nitride layer. The prior art solution to the problem was the fabrication of a protected drain-source device (PDS). As illustrated in FIG. 21a and FIG. 21b, a PDS device is equivalent to a variable threshold device having a thin silicon dioxide layer surrounded by a pair of peripheral transistors Q.sub.2 and Q.sub.3 having much thicker silicon dioxide gate insulator layers. By this means, a memory device may be fabricated having a BV.sub.DSS on the order of 30 volts. U.S. Pat. No. 3,719,866 discloses and claims such a device having a P-type channel region.
Unfortunately, the PDS device fabrication techniques of the prior art present certain severe drawbacks. Because of the fabrication techniques used, all of the transistors contained within an LSI chip having PDS devices are fabricated with a silicon dioxide/silicon nitride dual gate insulator layer. While this dual insulator layer suffices for the variable threshold memory element, it unfortunately causes a change in the threshold of the device. This change of threshold actually varies with time, causing a fixed threshold device containing such a dual layer insulator to be unstable.
Another problem in the fabrication of prior art devices is that, subsequently to the fabrication of PDS memory devices, additional processing steps are required which necessitate elevated processing temperatures, e.g., above 900.degree. C. These additional, high temperature processing steps cause degradation in the charge retention capability of the silicon nitride layer of the PDS device (e.g., the PDS device may store a charge for only a few months, rather than a few years as intended).